The present invention relates generally to a semiconductor device, and more particularly to a semiconductor device which generates internal voltages having different levels using an external voltage.
Generally, a semiconductor device such as DRAM generates and uses various internal power sources using an external power as a source. For example, in order to transfer data stored in a memory cell to a bit line without a voltage drop due to a threshold voltage, a DRAM generates a pumping voltage having a higher voltage level than that of the an external voltage by pumping the supplied external voltage. The DRAM then provides the generated pumping voltage to a word line.
A conventional circuit which generates such an internal voltage may be provided, as shown in FIG. 1, with a core voltage generating circuit 10 which generates a core voltage VCORE and a pumping voltage generating circuit 20 which generates a pumping voltage VPP.
The core voltage generating circuit 10 includes an activating unit 12 which outputs an activation signal VCORE_ACT in response to an external command signal, i.e. a RAS command signal RASB. The core voltage generating circuit 10 also includes a detecting unit 14 which compares and detects a potential difference between the core voltage VCORE fed back to the detecting unit 14 and a reference voltage VREF1 in response to the activation signal VCORE_ACT and outputs the detection result as a drive signal DRV. The core voltage generating circuit 10 includes a driving unit 16 which generates the core voltage VCORE by driving an external voltage VEXT in response to the drive signal DRV.
The pumping voltage generating circuit 20 includes an activating unit 22 which outputs an activation signal VPP_ACT in response to the RAS command signal RASB. The pumping voltage generating circuit 20 also includes a detecting unit 24 which compares and detects a potential difference between the pumping voltage VPP fed back to the detecting unit 24 and a reference voltage VREF2 in response to the activation signal VPP_ACT and outputs the detection result as a drive signal PPEA. The pumping voltage generating circuit 20 includes a pumping unit 26 which generates the pumping voltage VPP by pumping the external voltage VEXT in response to the drive signal PPEA.
The conventional semiconductor device including the internal voltage generating circuits 10 and 20 as described above activates a word line WL by supplying the pumping voltage VPP when an active command ACT is inputted synchronously with a clock signal CLK, and develops a bit line pair BL and /BL by supplying the core voltage VCORE after a charge sharing as shown in FIG. 2A.
At this time, the pumping voltage VPP level may drop as the pumping voltage VPP is supplied to the word line WL. The level pumping of the pumping voltage VPP may be performed after a point ‘T2’ as the detecting unit 24 cannot detect this drop of the pumping voltage VPP level within the period ‘T3’.
In other words, as shown in FIG. 2B, when the pumping voltage VPP level drops below the reference voltage VREF2 level at point ‘T1’, the pumping voltage VPP level is raised via the detecting unit 24 and the pumping unit 26. At this time, a series of operations occur including, detecting the level drop of the pumping voltage VPP at ‘T1’ through the detecting unit 24. The drive signal PPEA is then enabled and the pumping voltage VPP level is pumped through the pumping unit 26 which takes longer than a period ‘T3’. Thus, the pumping of the pumping voltage VPP level is actually performed after ‘T2’. The external voltage VEXT is consumed after ‘T2’ by the pumping of the pumping voltage VPP level.
Also, the driving unit 16 consumes the external voltage VEXT to maintain the core voltage VCORE level at the reference voltage VREF1 since the core voltage VCORE is supplied to the bit line BL or the bit bar line BLB from the point ‘T2’. In other words, after the point ‘T2’, the external voltage VEXT level drops due to the use of the core voltage VCORE.
As such, in the conventional semiconductor device, the level drop of the external voltage VEXT due to the pumping of the pumping voltage VPP and the level drop of the external voltage VEXT due to the driving of the core voltage VCORE are generated almost simultaneously with respect to the point ‘T2’.
However, when the external voltage VEXT is used in duplicate for the pumping of the pumping voltage VPP and the driving of the core voltage VCORE, a peak value of the external voltage VEXT level drop is instantly increased. This increase may generate a large amount of noise in the external voltage VEXT.
In this case, problems including the lowering of chip properties may occur eventually leading to a malfunction of the semiconductor chip.